`include "timescale.v"

module top_wb_aes(clk,reset,
                  wb_stb_i,wb_dat_o,wb_dat_i,wb_ack_o,
                  wb_adr_i,wb_we_i,wb_cyc_i,wb_sel_i,
                  wb_int_o);

input         clk;
input         reset;
input         wb_stb_i;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_ack_o;
input  [29:0] wb_adr_i;
input         wb_we_i;
input         wb_cyc_i;
input  [3:0]  wb_sel_i;
output        wb_int_o;

wire          load_i;
wire          decrypt_i;
wire [127:0]  data_i;
wire [127:0]  key_i;
wire  [127:0] data_o;
wire          ready_i;

wire [31:0] wb_adr_ii;
assign wb_adr_ii = wb_adr_i << 2;

wb_aes_controller wb_controller(
 .clk(clk),.reset(reset),
 .wb_stb_i(wb_stb_i),.wb_dat_o(wb_dat_o),.wb_dat_i(wb_dat_i),.wb_ack_o(wb_ack_o),
 .wb_adr_i(wb_adr_ii),.wb_we_i(wb_we_i),.wb_cyc_i(wb_cyc_i),.wb_sel_i(wb_sel_i),
 .load_o(load_i),.decrypt_o(decrypt_i),.data_o(data_i),.key_o(key_i),
 .ready_i(ready_o),.data_i(data_o)
 );

//this module reset: negedge sensitive
aes aes128(
 .clk(clk),.reset(~reset),
 .load_i(load_i),.decrypt_i(decrypt_i),.data_i(data_i),.key_i(key_i),
 .ready_o(ready_o),.data_o(data_o)
 );

assign wb_int_o = ready_o;

endmodule
